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High Performance Correlators

This is the Mark IV digital correlator board in use at MIT Haystack Observatory. It utilizes 32 VLSI chips and allows over 16,000 real lags to be computed at a rate of 64 million samples per second. For VLSI applications, 16 boards will be constructed in each correlator to handle 16 stations at 1 billion bits per second for each station at 32 complex lags. Each board is 50cm x 40cm in size -- a single one will replace an entire rack of Mark IIIA correlator equipment.

Haystack Correlator
This digital correlator is intended for use in interferometry applications in radio astronomy. This chip integrates, in addition to the corellator itself, many of the functions needed by a multiple antenna interferometry system. The die contains the equivalent of 512 real correlator channels, organized into 8 sections of 64 channels each. Each section can be configured into a 32 channel complex correlator. It also contains a phase generator configured into a 32 channel complex correlator. The phase generator circuit is also associated with each of the 8 sections. Internal muxing circuits will allow flexibility in interconnecting the correlator sections. The correlator contains a control register and a 16 bit asynchronous I/O port. The key features of this correlator IC are listed below:

Complex or Real Cross/Auto Correlation supported
64 Megasamples/second on 26 independant data streams
- 32 Megasamples/second if phase generators are used
Counter streaming sample registers to simplify crosscorrelation
2 bit, 4 level arithmetic supported
Optional valid bit per sample supported
512 lags, with many configuration options
8 on-chip 32 bit, 3 level, phase generators
8 on-chip level rotators
On-chip fractional bit delays of samples supported
24-bit accumulator stages
24-bit asynchronous bidirectional data port
Low Power
Fully cascadable
Integration can continue while data is output
CMOS compatible 1/O

Haystack correlator specifications (Postscript)
Haystack correlator specifications (Acrobat PDF)

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Quaint Correlator
This correlator chip accepts two data streams (A and B) at a maximum sample rate of 100 MHz. Samples from Stream A are successively delayed (in a 1024-stage internal shift register) and multiplied by the (undelayed) data from Stream B. Arithmetic is performed in 1024 individual multiplier/accumulators, operating in parallel. At the end of an integration period the data in the accumulators is parallel-loaded into 1024 output registers. New integration can begin immediately. The contents of the output registers can be shifted out at rates up to 20MHz, via a 32-bit tri-stating output port. The chip supports data multiplexing and all control signals are passed through the chip, to simplify cascading. The key features of this correlator IC are listed below:

Autocorrelation or Crosscorrelation
1024 lags
100 Megasamples/second
Double Nyquist sampling supported
3-level or 2-level arithmetic supported (+1,0,-1; +1,-1; or +1,0)
32-bit accumulator stages for 3 level operation
32-bit accumulator stages for 2 level operation
Low Power
Data and Control signals cascadable
Selectable auxiliary ports on both data inputs
Accumulator blanking supported
Integration can continue while data is output
CMOS and TTL compatible inputs

Quaint correlator specifications (Postscript)
Quaint correlector specifications (Acrobat PDF)

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JPL Correlator
Narrow Band Auto Correlator for the JPL Microwave LIMB Sounder was delivered in November 1991. The correlator contains 32 time-lag channels, each consisting of a biasing multiplier, 4 bit accumulator and a 24 bit counter. The inputs are 2-bit data words. The correlators are capable of maintaining a 25 Megasample/second input data rate for periods up to 1.78 seconds. Data can be output at a 10 MHz data rate. The chip consumes less than 10 mW/channel of average power.

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Aerocibo Correlator
This custom processor was completed for a 1 Gsample/sec spectrum analyzer to be used in radio astronomy work at Arecibo and Greenbank. Co-sponsors were NRL, NIAC, NRAO and NASA. The processor contains 1024 independent correlators and consumes 2 watts while operating at 100 MHz. The resulting die contained over 1.2 million transistors and was only 10 mm x 10 mm. The chip contains SEU immune circuitry in the control section.

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ULP Polarimetry Correlator
Sponsored by NASA GSFC, this high-speed digital cross correlator IC is used to detect the polarization state, or Stokes vector, by measuring the in- and quadrature-phase correlations between two orthogonally-polarized thermal microwave signals. The signals are received by a conventional dual-polarization radiometer, but are sampled at 500MHz and 3-level quantized before detection. The correlator IC computes cross products that are integrated for up to 2²⁴ clock cycles. The integration time is programmable with a step size of 2⁸ clock cycles. Targeted for eventual space-flight use, the correlator chip has been designed with radiation-tolerant architecture and will be fabricated using 0.35µ ULP CMOS logic operating at 1.0V or less (possibly down to 0.5V).

ULP Polarimetry Correlator specifications (Acrobat PDF)

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Orbiting HF RFI Monitor correlator
The Orbiting HF Radio Interference Monitor mission is a small, fast, cost-effective experiment package to demonstrate new spectral analysis technology in space and pave the way for future space-based low frequency astrophysical studies. Its sophisticated correlator provides thousands of spectral channels with a dynamic range not previously achieved with autocorrelator-based spectrometers. The heart of this instrument is a high-performance autocorrelator chip, which packs 1024 channels in a 1 cm by 1 cm VLSI chip. This chip represents an excellent example of NASA, DoD, National Observatory, and university collaboration and exploitation of NASA-developed technology.

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