CHIPS |
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| CHIPS |
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Error Correction 
CCSDS DecoderOriginally delivered as a chip set consisting of 4 custom 3um CMOS chips along with 3 commercially available memory chips, this decoder has become an international standard. The decoder is deployed throughout the CDOS network, the Deep Space Network (DSN) and is being used in direct downlink receiver stations designed by Code 500 at GSFC. A single chip flight qualified version is currently in design utilizing a commercial 0.35um CMOS technology and should be available soon. · Return to top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCSDS EncoderA CCSDS Reed Solomon encoder has been designed and fabricated to Military specifications and delivered to GSFC. 51fully functional processors packaged in flight packages were delivered. The yield on the flight-packaged parts was 82.5%. Two independent processors reside on each chip, where each processor performs 2,500 million operations per second with a 320 million bit per second data rate at MIL specification ranges. A moderate speed flight Reed Solomon encoder was also designed with a UTMC space qualified gate array that performs at a data rate of 200 Mbits/sec. The interleaving depth is programmable up to 8. This chip is currently flying on-board and is being designed into a number of future NASA missions including EOS-AM, NOAA, Landstat-7, WARP, XTE, TRMM and HST-'97. • Download the rs16 spec (PDF format) · Return to top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Edac 5A 5 error correcting Reed Solomon chip was designed for Ampex Corporation in 1.6 um CMOS. The chip was used in a military high performance tape drive and contained 140,000 transistors. A Reed Solomon decoder was designed for the Hubble Space Telescope ground station. This single chip 1.6 um CMOS design corrects up to 10 errors. The chip operation rate exceeded 1 billion operations per second. This processor has become the standard for error correction in the HDTV proposals. A flight qualified 5 error corrector utilizing the Institute's rad-tolerant techniques for space has been designed. This chip is at the heart of the solid state recorder installed on the Hubble Space telescope during the STS-82 mission in February, 1997. It is also being designed into the EOS-AM, LandSat 7 and NOAA missions. • Download the Edac5 spec (PDF format) · Return to top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hewlett Packard ECC12 high-performance Error Correction macrocells have been designed in HP's 1.6, 1.0 and 0.8 um CMOS processes. These ECC units have been used on the controller chips for several generations of HP disc drive products. The layout of the 0.8 um designs used a schematic driven automatic tiling system to assemble the base cells. · Return to top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . | ©2003 University of Idaho. All rights reserved. Disclaimer. |
