• Keynote Address 1
• Platform-Based System-on-Chip Design
  
• Design & Synthesis I
• Synthesis of Small and Fast Finite Field Multipliers for Field Programmable Gate Arrays
• Efficient Bit-Serial Constant Multiplication for FPGAs
• A Synthesis Scheme for Low Power Designs with Multiple Voltages Under Timing Constraints
• Automated Minimization of BTS Pass Networks
  
• Design & Synthesis II
• Low Power Driven High-Level Synthesis for Dedicated Architectures
• Selecting a Weighting Criteria for System Allocation
  
• Radiation Tolerant Electronics
• Analog Rad-Hard by Design Issues
• Radiation Hardness of Ultra Low Power CMOS VLSI
• Hardness By Design Techniques for Field Programmable Gate Arrays
  
• Analog
• A 1.2V 2.4GHz Integrated Direct Downconversion Receiver Front-End
• A Direct Digital Frequency Synthesizer Prototype for Space Applications
• Broadband Delta Sigma Modulator with 1 GHz Sampling Rate and Four-bit Quantizer in 0.18um CMOS Technology
• Design of a CMOS Low Noise Amplifier (LNA) at 5.8 GHz and Its Sensitivity Analysis
• Low-voltage, Wide gm Adjustment Range, Highly Linear BiCMOS OTA
  
• ASICs I
• An Ultra-Low Power, Radiation Tolerant, High Speed Correlator
• A Family of Analog and Mixed Signal VLSI ASICs for NASA Science Missions
  
• Keynote Address II
• MIT Lincoln Laboratory’s Low Power, High Performance, Fully Depleted SOI CMOS Process Technology
  
• Mixed Signal
• A Novel Asynchronous ADC Architecture
• A 12-bit DAC for Space Applications
• Asymmetrical Subranging R2R DAC in ULP
  
• ASICs II
• High Density Standard Cell Library
  
• Micro-Nano I
• The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic
• Piezoelectric Polyimide MEMS Process
• Magnetic Element Shape for Magnetic Random Access Memory (MRAM)
  
• Micro-Nano II
• Nano current charging algorithms for thin film lithium microbatteries
• Concept for a Micro Autonomous Ultrasonic Instrument (MAUI)
  
• Systems & Applications
• A Low-Power Microinstrument for Chemical Analysis of Remote Environments
• Focal Plane Array Sensor Readout Correction on a Reconfigurable Processor
  
• Power & Testing
• Parametric Timing Failures and Defect-based Testing in Nanotechnology CMOS Digital ICs
• Localizing Faults in Digital Chips using Steady-State Current Measurements
• Development and Testing of High-Voltage Devices Fabricated in Standard CMOS and SOI Technologies

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