TECHNOLOGY |
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CAMBR VLSI Technologies CAMBR's engineers and scientists are working closely with industry, government, and national laboratories to advance the state of the art these key areas:
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Ultra-Low-Power MicroelectronicsThe Ultra-Low-Power (ULP) program is aimed at reducing the power consumption of VLSI chips by one or two orders of magnitude. The cornerstone of the program is a low-voltage CMOS technology. The dynamic power consumption of CMOS chips is proportional to the square of the supply voltage; the ULP process reduces the supply voltage to 0.5V to achieve an optimal balance between static and dynamic power consumption. This requires a small change in an otherwise standard commercial process. Innovative circuit design is required to accurately control the switching threshold and to optimize the design for low-voltage operation. Papers for Ultra-Low-Power Microelectronics Requires Adobe Acrobat
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Radiation Tolerant MicroelectronicsThe goal of CAMBR's radiation tolerant microelectronics effort is to produce Radiation Tolerant (RT) VLSI chips from commercial processes. This is significantly less expensive than using a specialized, radiation-hard process, and so puts radiation tolerance within the reach of more designers. CAMBR has developed a combination of layout and circuit design techniques to achieve Single Event Latchup (SEL) immunity, and to mitigate Single Event Upset (SEU) and Single Event Transient (SET) effects. When we combine ULP and RT, we have genuine synergy: the ULP process technology significantly enhances Total Ionizing Dose (TID) immunity. CAMBR's RT features are captured in RT standard cell libraries, enabling radiation-tolerant chips to be synthesized from Hardware Description Language such as VHDL or Verilog, using commercial synthesis tools like Synopsys Design Compiler. Papers for Radiation Tolerant Microelectronics Requires Adobe Acrobat
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Reconfigurable ProcessorsReconfigurable Computing is an exciting new technology that promises to increase processing throughput without increasing clock rate and the associated dynamic power consumption. The idea is to build a processor that can rewire itself, under software control, to optimize its architecture for the problem at hand: to achieve "the performance of dedicated hardware with the flexibility of software." By using the same silicon in different ways for different phases of a processing task, we save size, weight and power. CAMBR is developing the Reconfigurable Data Path Processor (RDPP) chip which incorporates sixteen reconfigurable processing elements, a program memory and program controller, programmable interconnects, and programmable I/O and control blocks, to implement complex signal processing tasks. Information about our research can be found in our CHIPS pages. A key feature of the RDPP is extensibility. Multiple RDPP chips can be tiled to handle large-scale processing tasks with little or no cost in throughput. The target throughput for most tasks is 60 Msamples/second. The RDPP will be produced in CAMBR's radiation-tolerant CMOS technology. Papers for Reconfigurable Processors Requires Adobe Acrobat
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Error CorrectionWorking closely with NASA's Goddard Space Flight Center, CAMBR has developed several chips to implement error correction on spacecraft communication channels. Error correction encoders insert a small amount of redundancy into a data stream before it is transmitted. Error decoders examine the received data stream, and exploit the redundancy to detect and correct errors that have occurred in transmission. The CAMBR error correction chips implement the Consultative Committee for Space Data Systems (CCSDS) standard algorithms. For more information, visit our CHIPS pages. · Return to top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data CompressionAnother important area of collaboration between CAMBR and NASA Goddard has been signal and image data compression for spacecraft instruments. A compressed image takes up less storage space that a "raw" image. This helps us to stretch the storage capacity on a satellite and increase the amount of science data we can gather. Compressed data also reduces the burden on communication resources for downlink, saving power and optimizing the use of downlink bandwidth. Lossless Compression Lossless data compression removes redundancy in a signal, such as an image, and stores the signal in a more space-efficient manner. The signal or image can be exactly reconstructed from its compressed form. The Universal Source Encoder for Space (USES) chips implement the Rice algorithm for lossless compression. More information is available in the CHIPS section. Lossy Compression Lossy compression is able to achieve greater data volume reduction than lossless compression. The compressed image cannot be reconstructed exactly, but the designer can select the amount and kind of information lost in order to achieve the desired compression ratio. (Here we mean "information" in the strictest engineering sense; what is lost may not actually be information, as far as the user is concerned.) The increased compression rate makes lossy compression the technology of choice for many applications. CAMBR and NASA Goddard are developing the Bit Plane Encode (BPE), a highly versatile lossless compression chip. It can implement any transform technique based on 8x8-pixel blocks, including the Discrete Wavelet Transform, Discrete Cosine Transform, and Lapped Transform, with a data rate of 320 Mbits/second. The BPE can achieve very high, user-specified compression rates. A major advantage of the BPE is that the instrument designer can specify the desired bit rate; no external rate control is required. The Bit Plane Encoder is being implemented in a 0.25-micron, radiation-tolerant CMOS technology. · Return to top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CorrelatorsSpacecraft and astronomical instruments use high-speed signal correlation for interferometry, signal detection, and patter recognition. CAMBR has developed several high-speed correlator chips. Details are in the CHIPS section. · Return to top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CircuitsCAMBR's chip design expertise includes analog CMOS, full-and semi-custom digital CMOS, and asynchronous design. A series of innovative circuit concepts have arisen from CAMBR research. Papers for Circuit Concepts Requires Adobe Acrobat
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